1. Technical Field
Embodiments of the present invention relate to features of a versatile Multi-Port Memory Controller (MPMC) that can be included in a system to control access to memory from processors, devices, or buses.
2. Related Art
A conventional processor-based system includes a processor along with a memory, and one or more peripheral devices. The memory stores data and instructions for the computing system. The peripheral devices can include components such as graphics cards, keyboard interfaces, and network interface cards. The computing system can include a system bus to facilitate communication among the processor and peripheral devices and the memory.
With memory access provided through a system bus providing for processor and peripheral devices, arbitration must be performed to gain access to ports of the bus. However, on a shared bus, arbitration is a serial process. That is, a component must request bus access, be granted bus access to the exclusion of all other components, and then perform a memory transaction. The bus arbitration overhead may not allow the full bandwidth capabilities of the memory to be utilized. For instance, the memory is not being kept busy during the time when components are requesting and receiving access to the system bus.
Conventional processor-based systems use some form of memory controller in order to access memory devices and provide arbitration to the memory for the processor and peripherals. Requirements for a memory controller to communicate with different type components and bus structures can decrease bandwidth from the normal operation of a bus-based system. To address the need to configure a memory controller to provide maximum bandwidth when used with various processor systems, a programmable logic device such as an Field Programmable Gate Array (FPGA) has been used to create the memory controller. FPGAs can be used to provide a wide variety of these memory controllers, including single port and multi port memory controllers.
FIG. 1 shows a block diagram of an FPGA 102 that can be used as a memory controller. The FPGA 102 illustratively comprises programmable or configurable logic circuits or “blocks,” shown as CLBs 104, I/O Blocks (IOBs) 106, and programmable interconnects 108, as well as configuration memory 116 for determining the functionality of the FPGA 102. The FPGA 102 may also include an embedded processor block 114, as well as various dedicated internal logic circuits, illustratively shown as blocks of random access memory (“BRAM 110”), and digital clock management (DCM) blocks 112. For a memory controller, the components of the FPGA 102 can be used to control an external memory 150. Those skilled in the art will appreciate that the FPGA 102 may include other types of logic blocks and circuits in addition to those described herein.
The IOBs 106, the CLBs 104, and the programmable interconnects 108 may be configured to perform a variety of functions. Notably, the CLBs 104 are programmably connectable to each other, and to the IOBs 106, via the programmable interconnect 108. Each CLB slice in turn includes various circuits, such as flip-flops, function generators (e.g., look-up tables (LUTs)), logic gates, and memory. The IOBs 106 are configured to provide input to, and receive output from, the CLBs 104.
Configuration information for the CLBs 104, the IOBs 106, and the programmable interconnect 108 is stored in the configuration memory 116. The configuration memory 116 can include static random access memory (SRAM) cells. A configuration bit stream to program the configuration memory 116 can be produced from the program memory 120.
The IOBs 106 can include transceiver circuitry configured for communication over any of a variety of media, such as wired, wireless, and photonic, whether analog or digital. The DCM blocks 112 provide well-known clock management circuits for managing clock signals within the FPGA 102, such as delay lock loop (DLL) circuits and multiply/divide/de-skew clock circuits.
The processor block 114 comprises a microprocessor core, and typically associated control logic. Notably, such a microprocessor core may include embedded hardware or embedded firmware or a combination. A soft microprocessor 134 may be implemented using the programmable logic of the FPGA 102 (e.g., CLBs 104 and IOBs 106).
As one example, the FPGA used to make an MPMC can be one selected from the Virtex-4 family of products, commercially available from Xilinx, Inc. of San Jose, Calif.
To enable high data-rate communications (e.g., 1200 megabits per second full duplex), the FPGA can be configured as an MPMC with built-in arbitration logic. A typical MPMC will have a fixed number of ports to communicate with components connecting to a memory device. For example, the MPMC may include a port for communicating directly with a central processing unit (CPU) (e.g., an instruction-side processor local bus) and/or a port for communicating with a system bus.
Current MPMC designs have performance issues because of their fixed or non-flexible implementation or architecture. Notably, the systems have a fixed implementation because the port types cannot be changed, and the number of ports remains fixed. Further, they have a fixed arbitration scheme. The systems tend to have port connections to two buses, one for high-speed entities, and one for low-speed entities. The implementation of each of these entities affects the performance such that the lowest performing device on each bus sets the highest frequency possible on that bus. Some system ports are typically dedicated for connection to a CDMAC to allow for direct memory access. Current systems therefore can suffer performance degradation depending on design constraints.
It is desirable to define topologies to efficiently use the components of an FPGA to develop a memory controller. In particular, it is desirable to provide an MPMC that can allow source code to be efficiently changed dynamically to handle a desired number of ports, while maximizing system performance and providing compatibility with a number of different components including peripherals and memory devices that can be connected to the memory controller.